1. Field of the Invention
The present invention relates generally to circuitry which may be used in field programmable gate arrays (FPGA), and more particularly to circuitry for zero power AND or NOR gates.
2. Description of the Related Art
FIG. 1 illustrates typical PLD circuitry. As shown, the PLD has multiple inputs (I.sub.0 -I.sub.2), each connectable to one of a series of AND gates. The output of each AND gate then provides a product term. The actual components used in the PLD are NOR gates, but by inverting the inputs to the NOR gate circuitry, the AND gates of FIG. 1 can be formed. The output of the AND gates are connected through OR gates to provide outputs for the PLD. The outputs of the PLD are further fed back through a register to provide additional inputs for the AND gates. Although a limited number of inputs to the AND gates are shown in FIG. 1, a typical PLD provides approximately fifty inputs to a single AND gate enabling the PLD to have a wide decoding capability.
FIG. 2 illustrates components typically included in an FPGA. As shown, the typical FPGA includes input/output buffers (IOBs), an array of configurable logic blocks (CLBs), resources for interconnection of the CLBs, and a configuration memory. The IOBs are arranged around the perimeter of the device and provide an interface between internal components of the FPGA and external package pins. Resources for interconnection of the CLBs include interconnect lines, programmable interconnect points (PIPs) and switch matrixes made up of PIPs. Inputs and outputs of a CLB are connectable to other CLBs, or to IOBs using the interconnect lines and switch matrixes. PIPs as well as the switch matrixes are programmed to make connections by bits stored in the configuration memory.
Each of the CLBs in the array include on the order of 4 look up tables. The look up tables are made up of decoding logic addressing a group of memory cells. Each look up table typically receives approximately a 4 bit input and provides a single bit output from a memory cell. Although each look up table can be programmed to form an AND gate or NOR gate, with only 4 inputs to each look up table the decoding ability at each stage in an FPGA is very limited as compared with a PLD which has potentially hundreds of inputs connected to a single AND gate.